The semiconductor industry has relied on scaling/reducing device feature size in order to boost performance and increase transistor density. The continued device performance improvement due to scaling has seen the introduction of unique technologies such as semiconductor on insulator (e.g., SOI and GeO), stressor such SiGe, SiC, to improve mobility at the 90 nm node, epitaxial regrowth of source and drain (raised source and drain), high-k metal gate (HKMG) at the 45 nm node, and 3D structures such as FinFETs and trigates at the 22 nm node.
However, maintaining the device performance and good short channel control is quite challenging beyond the 14 nm technology node. New materials (e.g., III-V semiconductors, Ge, SiGe, graphene, MoS2, WS2, MoSe2, and WS2) and new integration schemes (e.g., nanowires) are needed. Nanowires offer scaling of feature size, good short channel control, and enhancement in the device electron mobility, hence enhancement in device speed.